• Compliant with DisplayPort specification version 1.2 and Embedded DisplayPort (eDP) specification version 1.3.

  • Support 2 Main Link Lanes at either 1.62Gb/s or 2.7Gb/s link rate

  • Support ITU-R 601 or ITU-R 656 compatible YCbCr 4:2:2 output format with embedded syncs or discrete syncs. Support resolution up to 1280 x 720@60Hz for YCbCr 4:2:2 output

  • HDCP engine compliant with HDCP 1.3 specification with internal HDCP Keys

  • On-chip Audio Decoder which support 2 channel IIS/S/PDIF audio output

  • Support RGB to YCC conversion in ITU-R BT.601 and 709 color space

  • Embedded MCU to handle the control logic

  • Support device boot up by automatically loading firmware from on-chip flash Boot ROM

  • Integrated EDID Buffer

  • Supports Enhanced Framing Mode

  • Fast and full Link Training for embedded DisplayPort system

  • Support eDP Authentication: Alternative Scramble Seed Reset and Alternative Framing

  • 2 work modes: connect 27MHz crystal, inject 27MHz clock

  • DP input detection supported

  • Support RGB to YCC conversion in ITU-R BT.601 and 709 color space

  • Support Auto Power Saving mode and low stand-by current

  • Support Spread Spectrum Clocking (de-spreading) for EMI reduction

  • DP AUX channel and IIC slave interface are available for firmware update and debug

  • Low power architecture

  • RoHS compliant and Halogen free package

  • Offered in 40-Pin QFN package (6 x 6 mm)


Chrontel’s CH7518 is a low-cost, low-power semiconductor device that translates the DisplayPort signal to the BT656 or 8 bit YCbCr 4:2:2 signal. This innovative DisplayPort receiver with an integrated BT656 encoder is specially designed to target the Notebook/Ultrabook, tablet device and automobile entertainment device. Through the CH7518’s advanced decoding / encoding algorithm, the input DisplayPort high-speed serialized multimedia data can be seamlessly converted to BT656 video and IIS or SPDIF audio output.

The CH7518 is compliant with the DisplayPort Specification 1.2 and the Embedded DisplayPort Specification version 1.3. With internal HDCP key Integrated, the device support HDCP 1.3 specifications. In the device’s receiver block, which supports two DisplayPort Main Link Lanes input with data rate running at either 1.62Gb/s or 2.7Gb/s, can accept RGB digital formats in either 18-bit 6:6:6 or 24-bit 8:8:8, and converted the input signal to 8 bit YCbCr output signal up to 1280 x 720@60Hz. Leveraging the DisplayPort’s unique source/sink “Link Training” routine, the CH7518 is capable of instantly bring up the video display to the device of BT656 input when the initialization process is completed between CH7518 and the graphic chip.

With sophisticated MCU and the Boot ROM embedded, CH7518 support auto-boot and EDID buffer. After the configuration by firmware, which is auto loaded from Boot ROM, CH7518 can support DP input detection, and determine to enter into Power saving mode automatically.







Input Interface eDP/DP

Output Interface TTL / BT656

Audio Interface IIS, SPDIF

Output Other features No

Package Type QFN40


Part Number Package Type Operating Temperature Range Minimum Order Quantity

CH7518A-BF 40 QFN, Lead-free Commercial : -20 to 70°C 490/Tray

CH7518A-BFI 40 QFN, Lead-free Industrial : -40 to 85°C 490/Tray











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