CH7010

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特征

  • DVI Transmitter up to 165M pixels/second

  • DVI low jitter PLL

  • DVI hot plug detection

  • TV output supporting graphics resolutions up to 1024x768 pixels

  • Programmable digital interface supports RGB and YCrCb

  • True scale rendering engine supports underscan in all TV output resolutions

  • Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering

  • Support for all NTSC and PAL formats

  • Provides CVBS, S-Video and SCART (RGB) outputs

  • TV connection detect

  • Programmable power management

  • 10-bit video DAC outputs

  • Fully programmable through serial port

  • Complete Windows and DOS driver support

  • Low voltage interface support to graphics device

  • Offered in a 64-pin LQFP package

描述

The CH7010 is a display controller device which accepts a digital graphics input signal, and encodes and transmits data through a DVI (DFP can also be supported) or TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide variable voltage data port which supports five different data formats including RGB and YCrCb.

The DVI processor includes a low jitter PLL for generation of the high frequency serialized clock, and all circuitry required to encode, serialize and transmit data. The CH7010 comes in versions able to drive a DVI display at a pixel rate of up to 165MHz, supporting UXGA resolution displays. No scaling of input data is performed on the data output to the DVI device.

The TV-Out processor performs non-interlace to interlace conversion with scaling and flicker filters, and encode the data into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to enable superior text display. Eight graphics resolutions are supported up to 1024 by 768 with full vertical and horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. Support is provided for RGB bypass mode which enables driving a VGA CRT with the input data.

结构图

数据表

 Click here to open the CH7010B Full Data Sheet.

应用说明


  •   Crystal Oscillator, AN-06.pdf (50 KB, 7/26/01)

  •   CRT discharge protection, AN-38.pdf

  •   CH7010A Registers Read/Write Operation, AN-41.pdf.

  •   PCB Layout and Design Considerations for CH7010A TV Output Device, AN-44.pdf.

  •   Recommendation of Composite & S-Video in single connector for CH7010, AN-46.pdf.

  •   Composite & S-Video in Single Connector for CH7010A Using DACs Switching Method, AN-48.pdf.

  •   Optimizing Operating Temperature for CH7010 DVI/TV Output Device, AN-53.pdf.

  •   A PCB Design Guideline to Prevent DVI Signaling Power-Reverting in CH7010A, AN-57.pdf.

  •   CH7010A SDTV/HDTV Encoder TV Connection Detection, AN-60.pdf.

  •   DACs Connection Detection of CH7010 Encoders, AN-71.pdf.

技术报告


  •   Input/Output Timing Diagram of CH7010 TV Encoders, TB-29.pdf (27 KB)

  •   Explanation for the Flickering Display Using Multi-sync TV in PAL Modes, TB-34.pdf (17 KB, 5/8/01)

  •   A Guideline to Measure Crystal and Color-Burst Frequencies, TB-37.pdf (20 KB, 9/17/01)

  •   New Method to Improve CH7010A REv. C/D PLL Stability, TB-38.pdf.

  •   DVI Output Eye Diagrams of CH7010A vs. CH7010B, TB-41.pdf.

  •   PCB Design Considerations of DAC outputs with Multiple Video Formats, TB-45.pdf.

  •   Limitation of SDTV Encoder Scaling Engine, TB-47.pdf (7/2/04)

规格

Input Interface  DVO , TTL/Digital RGB, TTL/YCbCr

Output Interface  DVI, CVBS , S-Video, SCART

Audio Interface   No

Other features  Scaler, Line Buffer

Package Type  LQFP64

订单信息

Part Number   Package Type     Number of Pins  Voltage Supply

CH7010B-TFLead Free - LQFP643.3V

CH7010B-TF-TRLead Free - LQFP in Tape & Reel643.3V


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