CH7304

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特征


  • Single LVDS transmitter

  • Supports pixel rate up to 100M pixels/sec

  • Supports up to SXGA resolution (1208 x 1024)

  • LVDS low jitter PLL

  • LVDS 24-bit or 18-bit output

  • 2D dither engine for 18-bit output

  • Panel protection and power down sequencing

  • Programmable power management

  • Fully programmable through serial port

  • Complete Windows and DOS driver support

  • Variable voltage interface to graphics device

  • Offered in a 64-pin LQFP package

描述

The CH7304 is a Display Controller device, which accepts a graphics data stream over one 12-bit wide variable voltage (1.1V to 3.3V) port. The data stream outputs through an LVDS transmitter to an LCD panel. A maximum of 100M pixels per second can be output through a single LVDS link.

The LVDS transmitter supports 24-bit panels; it also includes a programmable dither function for support of 18-bit panels. Data is encoded into commonly used formats, including those detailed in the OpenLDI and the SPWG specification. Serialized data output on four differential channels.

结构图

数据表

暂无信息

应用说明

  •   Crystal Oscillator, AN-06.pdf (50 KB, 7/26/01)

  •   Guideline to the Operation of EMI Emission Reduction of CH7304, AN-59.pdf (7/15/02)

  •   PCB Layout and Design Considerations for CH7304 Single LVDS Transmitter, AN-65.pdf (2/12/03)

技术报告

 LVDS Dithering, TB-44.pdf (8/13/03)

规格

Input Interface DVO , TTL/Digital RGB, TTL/YCbCr

Output Interface LVDS

Audio Interface  No

Other features  No

Package Type  LQFP64

订单信息

暂无信息

视频

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