· Compliant with DisplayPort Alternate Mode on USB Type C standard
· Compliant with DisplayPort Specification version 1.3 and Embedded DisplayPort (eDP) Specification version 1.4
· Support two link lane at 1.62Gbps,2.7Gbps (HBR) or 5.4Gbps (HBR2) link rate
· Automotive DP input signal detection
· DP_BR signaling modes supported
· Support Analog RGB output for VGA with Triple 9-bit DAC up to 240MHz pixel rate. Sync signals can be provided in separated or composite manner. Support VESA and CEA timing standards up to 2048x1536@60Hz with reduced blanking
· VGA output is compliant with VESA VSIS v1r2 specification
· DAC connection detection supported
· USB Power Delivery control module supported with HPD to PD converter integrated
· DisplayPort receiver auto equalization supported for the compensation of input signal attenuation
· Active DDC buffer and related control register integrated
· IIC-over-AUX transaction supported
· Single 3.3V power supply with regulator integrated
· Embedded MCU to handle the control logic
· USB billboard module integrated
· USB 2.0 PHY supported with internal switch for data/file transport
· Support device boot up by loading firmware from On Chip Flash automatically, integrated EDID Buffer
· MCCS bypass supported
· DP AUX channel and IIC slave interface are available for firmware update and debug
· Support Auto Power Saving mode and low stand-by current
· Anti-back drive support
· Low power architecture
· RoHS compliant and Halogen free package
· Offered in 48-Pin QFN package (6 x 6 mm)
Chrontel’s CH7212 is a low-cost, low-power semiconductor device that translates the DisplayPort signal to VGA through the USB Type-C connector. This innovative USB Type-C based DisplayPort receiver with an integrated VGA Transmitter is specially designed to target the USB Type-C to VGA converter, adopter and docking device. Through the CH7212’s advanced decoding / encoding algorithm, the input DisplayPort high-speed serialized multimedia data can be seamlessly converted to VGA output.
The CH7212 is compliant with the DisplayPort specification version 1.3 and the Embedded DisplayPort Specification version 1.4. In the device’s receiver block, which supports two DisplayPort Main Link Lanes input with data rate running at 1.62Gb/s, 2.7Gb/s or 5.4Gb/s, can accept RGB digital formats in either 18-bit 6:6:6 or 24-bit 8:8:8, and converted the input signal to VGA output up to 2048x1536@60Hz with reduced blanking. Leveraging the DisplayPort’s unique source/sink “Link Training” routine, the CH7212 is capable of instantly bring up the video display to the VGA monitor when the initialization process is completed between CH7212 and the graphic chip.
The DACs are based on current source architecture. And the VGA output meet VESA VSIS v1r2 clock jitter target. With sophisticated MCU and the on-chip Flash, CH7212 support auto-boot and EDID buffer. After the configuration by firmware, which is auto loaded from the Flash embedded, CH7212 supports DisplayPort input detection, DAC connection detection and determine to enter into power saving mode automatically.
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